CVE-2018-12126

Public on 2019-05-07
Modified on 2019-08-27
Description
Modern Intel microprocessors implement hardware-level micro-optimizations to improve the performance of writing data back to CPU caches. The write operation is split into STA (STore Address) and STD (STore Data) sub-operations. These sub-operations allow the processor to hand-off address generation logic into these sub-operations for optimized writes. Both of these sub-operations write to a shared distributed processor structure called the 'processor store buffer'. As a result, an unprivileged attacker could use this flaw to read private data resident within the CPU's processor store buffer.
Severity
Medium
CVSS v3 Base Score
6.5
See breakdown

Affected Packages

Platform Package Release Date Advisory
Amazon Linux 2 libvirt 2019-08-23 03:34 ALAS2-2019-1274
Amazon Linux 2 kernel 2019-05-07 22:39 ALAS2-2019-1205
Amazon Linux 1 qemu-kvm 2019-08-07 23:12 ALAS-2019-1260
Amazon Linux 1 kernel 2019-05-07 22:54 ALAS-2019-1205

CVSS Scores

Score Type Score Vector
Amazon Linux CVSSv3 6.5 CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N
NVD CVSSv2 4.7 AV:L/AC:M/Au:N/C:C/I:N/A:N
NVD CVSSv3 5.6 CVSS:3.0/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:N/A:N